Complexity Analysis of a Cache Controller for Speculative Multithreading Chip Multiprocessors

Although many performance studies of memory speculation mechanisms in speculative multithreading chip multiprocessors have been reported, it is still questionable whether the mechanisms are complexity effective and worth to implement. In this paper, we perform a complexity analysis of a cache controller designed by extending an MSI controller to support thread-level memory speculation. We model and estimate the delay of logic on critical paths and additional area overhead to hold additional control bits in cache directory. Our analysis shows that for many protocol operations, area overhead occupies more than half of the total delay. This area overhead is however smaller than the delay for accessing and comparing cache tags. When the protocol operations are performed in parallel with tag comparison, the critical path latency is increased by 11%. Overall, our results show the cache controller can be implemented with cycle time of less than 22 [FO4], and can be made faster if we further pipeline the protocol operations.